1. Technical Field
The present invention pertains to sensor calibration. In particular, the present invention pertains to an automatic calibration for a temperature sensor of a memory device.
2. Discussion of the Related Art
Memory devices are utilized to store information for various applications. A commonly utilized memory device includes a dynamic random access memory (DRAM). These types of memory devices store information in memory cell arrays that are configured in a matrix of intersecting rows and columns. The rows are commonly referred to as word lines. Each memory cell generally includes a storage capacitor to hold a charge and a transistor to access the charge of the capacitor. The charge may be a high or low voltage potential (referred to as a data bit), thereby providing the memory cell with two logic states. The memory cells of the DRAM must be refreshed periodically due to leakages within the capacitors storing the charges (or bits).
Generally, semi-conductor wafers include a plurality of chips or circuits (e.g., a Dynamic Random Access Memory (DRAM) wafer may include five-hundred chips). An exemplary chip or memory device is illustrated in FIG. 1. Specifically, each chip or memory device 2 (e.g., Dynamic Random Access Memory (DRAM)) includes a memory cell array 4, a temperature sensor 12 and a trim or calibration register 16. The memory cell array stores information or data and is substantially similar to the memory cell array described above. Since memory device operation may vary with temperature, the temperature sensor is utilized to measure the temperature of a corresponding chip. The temperature sensor includes a status register 14 to provide status bits or a code indicating the temperature sensor status in response to a temperature measurement. Trim register 16 stores calibration results for the temperature sensor as described below. The temperature sensor receives a trim or calibration setting from a test unit, and provides status bits or a code in status register 14 to indicate the temperature sensor status in response to a temperature measurement.
Basically, the status bits change states or values in response to the measured temperature in order to provide an indication of that temperature. Referring to FIG. 2, the temperature sensor status bits include states or values one through seven (e.g., ‘001’ to ‘111’ as indicated by the three status bits in FIG. 2) each associated with a corresponding temperature or temperature range. As the temperature increases, the status bits transition from state seven (e.g., status bit values of ‘111’) toward state one (e.g., status bit values of ‘001’) in accordance with the measured temperature. In other words, the status bits indicate the state corresponding to the temperature or temperature range encompassing the measured temperature. By way of example only, a transition of the status bits from state five (e.g., status bit values of ‘101’) to state four (e.g., status bit values of ‘100’) indicates detection of a reference temperature.
The temperature sensor of each chip needs to be calibrated with respect to the reference temperature to ensure uniform temperature measurements. In order to accomplish this calibration, a trim or calibration value is determined for temperature sensor 12 of each chip to enable the temperature sensors to provide status bits switching between the same states in response to detection of the reference temperature. In other words, each temperature sensor needs to provide status bits transitioning between the same states (e.g., between states five and four as viewed in FIG. 2) in response to detection of the reference temperature. The trim or calibration value achieving this result typically varies for each temperature sensor due to manufacturing or hardware fluctuations among the temperature sensors.
Currently, temperature sensor trimming or calibration is performed for a reference temperature of approximately 88° C. In particular, the ambient environment for each temperature sensor is set to approximately 88° C. Temperature sensors of several chips (e.g., on a wafer) are preferably calibrated in parallel. A trim or calibration value is provided to each temperature sensor 12 from a test unit. The temperature sensors detect the temperature and the resulting three bit status values are retrieved by the test unit from each status register 14 of the temperature sensors. The trim value and resulting status values are stored by the test unit external of the chips. The trim value is incremented by the test unit, where the above sequence is repeated numerous times (e.g., typically at least forty times) for each temperature sensor in order to identify the appropriate trim value for that temperature sensor. The number of sequence iterations performed is based on the quantity of temperature sensor trim or calibration values, and the quantity of temperature measurements needed to determine the appropriate trim values for the temperature sensors. These trim values may vary among the temperature sensors due to hardware fluctuations as described above.
After completion of the sequence iterations, the stored information (e.g., trim and status values) is analyzed by the test unit in a post-processing phase to determine the appropriate trim or calibration value for each temperature sensor. This is accomplished by identifying the trim value associated with the desired transition of the three bit status value for the reference temperature (e.g., the trim value associated with the status value change from five to four as viewed in FIG. 2). The identified trim values (e.g., seven bit code or value) are subsequently transferred to a fuse converter for burning or hard coding onto chips 2 in corresponding trim registers 16 (e.g., fuse registers, etc.). The resulting trim or calibration values stored in trim registers 16 are subsequently used by the corresponding temperature sensors.
The technique described above suffers from several disadvantages. In particular, the technique is time intensive and tends to produce inaccurate results. Further, since the temperature sensors are calibrated in parallel, the calibration sequence is repeated numerous times for each temperature sensor. Thus, the calibration may be performed for temperature sensors even after the appropriate calibration or trim value has been utilized in a prior iteration, thereby performing unnecessary calibration steps and increasing the time for the calibration. This further provides additional and unnecessary information for the post processing phase and wastes resources. Moreover, the processing for the calibration is performed external of the chip, thereby requiring additional tasks of transferring information between the chip and external test unit that further complicate and increase the time for the calibration. In addition, the above technique requires the test unit to perform or issue two commands or steps (e.g., provide a trim or calibration value and retrieve status bits) for each iteration. This utilizes substantial processing time of the test unit and complicates the procedure.